Thick Copper, Thin Margins: How to handle Cu Thickness in complex PCB designs

Specifying copper (Cu) thickness correctly is crucial in PCB design, especially when dealing with filled vias or IPC Class 3 requirements. Design complexity—like plugged through holes or Cu-filled microvias—can drive Cu thickness beyond manufacturable limits. What to do?

terho

A good base on how to specify your Cu thickness is stated in IPC. IPC A-600 covers the basic cu thicknesses for both inner and outer-layers in section 3.2.3 and 3.2.4 

A buried plated inner layer should in general be treated as a plated outer layer as in 3.2.3. This is because the plating is the same as for outer layers. Alot of manufacturers in this case are choosing the 12um foil as the start for these layers. 

In the case of standard multilayers with only PTH holes or even micro vias, this is not an issue. However, it’s easy to follow IPCs guidelines, just remember that the track/gap capabilities always go hand in hand with the Cu thickness. 

Plugged through holes, how do you dig into them?
The challenges start when you have a product with either type VII plugged through holes, either in a buried layer or between the outer layers.  The same type of problem also occurs when using filled microvias. Especially if you have a product that needs IPC class 3 plating thicknesses, either for reliability or for press fit purposes. 

So, you start with the 12um foil, add 20um or 25um in the plugged through holes, then additionally add another 20 or 25 ums for normal vias. 12+25+25. We are suddenly up on thicknesses 50-65um for either the buried or outer layer. As you understand, nobody can etch 75um track and gaps in such thick Cu. A Similar problem occurs for Cu filled microvias, though not as thick as 60um, but close. 

So how is this sorted out through manufacturing? 

There are 4 ways to solve these challenges: 

  1. Use a plugging method with screenprint, and only 1 plating for both plugged and non-plugged holes. However, it will require a cap plating which adds only 18um additional Cu. This gives us: 12+25+18, still quite high for 75um track and gap. Another challenge that might be added is the fact that, when using this screen print method, you easily get air into the plug, and the filling might be insufficient (as mentioned in my previous post about plugging). 
  2. Avoid open-through vias, meaning, if possible, plug all holes. This leaves us at the same Cu thickness as above, but we can do the plugging in a vacuum machine. 
  3. After plating and filling the plugged holes, the manufacturer does an additional etch process after hardening the plug. This is just to reduce the Cu thickness on the surface. After this, you would also need a planarizer (sanding/mechanical removal) of the protuberance plug, because you have removed Cu around it by pre-etching the surface. Here you must be careful, so you do not smear the plug out on top of the pre-etched Cu and prevent further Cu-plate. 
  4. Choose a 5um Cu foil from the beginning. 

To summarize these options:  

  • Provide enough thickness tolerance to the type VII plugged or microvia filled Cu layer. This is because there might be differences depending on which production flow the manufacturing site has.  
  • Avoid impedance tracks on these layers, as there are both thickness differences, and the etch profile might be worse due to thick Cu.  
  • Please do use minimum gaps only where this is needed. A tiny gap is always harder to make than a tiny track. 

Consider if there is a need of critic section Wrap plating in IPC 6012, 3.6.2.11and 3.6.2.11.1 

If you have any questions, feel free to reach out to Terho at: terho.koivisto@confidee.com

Thick Copper, Thin Margins: How to handle Cu Thickness in complex PCB designs

Written by: Terho Koivisto

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